1. Field of the Invention
The present invention relates to a high-speed duty-cycle correction circuit, and more particularly to a high-speed duty-cycle correction circuit which is applied to an input and an output exposed from an outer surface of a semiconductor chip, or to an input and an output of each of a delay-locked loop (DLL) and a phase-locked loop (PLL) in the semiconductor chip to correct a duty-rate.
2. Description of the Related Art
In order to reduce a size of a basic cell of a dynamic random access memory (DRAM), research for a process for reducing a capacitor cell size of a DRAM, such as 4×nm, 3×nm, etc., has been conducted. Although the basic cell is significantly related to the DRAM size, due to the limits of DRAM process development, it has been demanded to reduce even a size of a DRAM internal circuit. Further, as mobile equipments have been pervasive widely, a memory has been required to include a circuit for rapidly switching from a power-down mode for low-power consumption to a normal operation mode, for high-speed and low-power consumption. In particular, in a clock generator which has an effect on power consumption, such as a delay-locked loop circuit, a phase-locked loop circuit, etc., a duty-cycle correction circuit has been required to have a small size as well as to perform a rapid switching.
For securing an effective data portion of semiconductor memory output data as much as possible, an inner clock used in a semiconductor memory must be guaranteed a 50:50 duty-rate symmetrically. However, since input and output clocks may be asymmetrical, there is a need for providing a duty-cycle correction circuit which can correct it.
An analog scheme of two schemes which are used in both a duty-cycle detector and a controller has a defect that it takes too long to compensate a duty error. So, it is not suitable to a system including a memory which is required to perform a rapid switching from a power-down mode to a normal operation mode. A digital control scheme may generate a duty-rate error due to a non-linear characteristic of a delay cell used in a time/digital converter, and its production cost become higher because of the time/digital converter size.